entity loads is

	port (
		entrada : in bit_vector(31 downto 0);
		saida : out bit_vector(31 downto 0);
		seletor : in bit_vector(1 downto 0)
	);
end loads;

architecture arc_loads of loads is
	signal bitLb : bit_vector(31 downto 0);
	signal bitLh : bit_vector(31 downto 0);
begin

	bitLb(31 downto 8) <= "000000000000000000000000" when entrada(7) = '0' else 
             "111111111111111111111111";	
	bitLh(31 downto 16) <= "0000000000000000" when entrada(15) = '0' else 
             "1111111111111111";
	bitLb(7 downto 0) <= entrada(7 downto 0) when seletor = "10" else
						"00000000" when seletor /= "01";
	bitLh(15 downto 0) <= entrada(15 downto 0) when seletor = "01" else
						"0000000000000000" when seletor /= "10";
	saida <= bitLb when seletor = "10" else
			bitLh when seletor = "01" else
			entrada;
		
end arc_loads;

		

		
			